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Features
* High Density, High Performance Electrically Erasable Complex
Programmable Logic Device - 128 Macrocells - 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell - 68, 84, 100, 160-pins - 7.5 ns Maximum Pin-to-Pin Delay - Registered Operation Up To 125 MHz - Enhanced Routing Resources Flexible Logic Macrocell - D/T/Latch Configurable Flip Flops - Global and Individual Register Control Signals - Global and Individual Output Enable - Programmable Output Slew Rate - Programmable Output Open Collector Option - Maximum Logic utilization by burying a register within a COM output Advanced Power Management Features - Automatic 100 A Stand-By for "Z" Version (Max.) - Pin-Controlled 100 A Stand-By Mode (Typical) - Programmable Pin-Keeper Inputs and I/Os - Reduced-Power Feature Per Macrocell Available in Commercial and Industrial Temperature Ranges Available in 84-pin PLCC and 100-pin PQFP and TQFP and 160-pin PQFP Packages Advanced Flash Technology - 100% Tested - Completely Reprogrammable - 100 Program/Erase Cycles - 20 Year Data Retention - 2000V ESD Protection - 200 mA Latch-Up Immunity JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported Fast In-System Programmability (ISP) via JTAG PCI-compliant 3.3 or 5.0V I/O pins Security Fuse Feature
*
High Performance E2 PLD ATF1508AS/Z
*
* * *
* * * * *
Enhanced Features
* * * * * * * * * * *
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms D - Latch Mode Combinatorial Output with Registered Feedback within any Macrocell Three Global Clock Pins ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O Fast Registered Input from Product Term Programmable "Pin-Keeper" Option VCC Power-Up Reset Option Pull-Up Option on JTAG Pins TMS and TDI Advanced Power Management Features - Edge Controlled Power Down "Z" - Individual Macrocell Power Option - Disable ITD on Global Clocks, Inputs and I/O for "Z" Parts
Rev. 0784C-4/98
1
84-Lead PLCC Top View
I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O
100-Lead TQFP Top View
I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O VCCIO
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O/PD1 VCCIO I/O/TDI I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO
100-Lead PQFP Top View
I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
I/O I/O/PD2 I/O N/C N/C N/C N/C I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O I/O VCCIO I/O I/O I/O I/O I/O N/C N/C N/C N/C I/O I/O I/O
GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O
160-Lead PQFP Top View
I/O I/O I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O I/O I/O I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O
N/C N/C N/C N/C N/C N/C N/C VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O/TMS I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O N/C N/C N/C N/C N/C N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
N/C N/C N/C N/C N/C N/C N/C GND I/O/TDO I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O/TCK I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O N/C N/C N/C N/C N/C N/C N/C
I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O
2
ATF1508AS/Z
I/O GND I/O N/C N/C N/C N/C I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O GND VCCINT I/O I/O/PD1 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O N/C N/C N/C N/C I/O VCCIO I/O
ATF1508AS/Z
Block Diagram
6 to 12
3
Description
The ATF1508AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel's proven electrically erasable Flash memory technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508AS's enhanced routing switch matrices increase usable gate count, and increase odds of successful pin-locked design modifications. The ATF1508AS has up to 96 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 128 macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term, which goes to a regional bus. Cascade logic between macrocells in the ATF1508AS allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs. Unused Macrocells are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the contents of the ATF1508AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse. The ATF1508AS device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG's Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Product Terms and Select MUX Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/CASCADE Logic The ATF1508AS's logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay. The macrocell's XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. Flip Flop The ATF1508AS's flip flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flowthrough latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can either be the Global CLK Signal (GCK) or an individual product term. The flip flop changes state on the clock's rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop's asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Output Select and Enable The ATF1508AS macrocell output can be selected as registered or combinatorial. The buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configuration all the macrocell resources are still available, includ-
4
ATF1508AS/Z
ATF1508AS/Z
ing the buried feedback, expander and CASCADE logic. The output enable for each macrocell can be selected as one of the global OUTPUT enable signals. The device has six global OE signals. Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 128 macrocells. The Switch Matrix in each Logic Block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the Logic Block. Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell's product terms. The 16 foldback terms in each region allows generation of high fan-in sum terms (up to 21 product terms) with a small additional delay. 3.3V or 5.0V I/O Operation The ATF1508AS device has two sets of V CC pins viz, VCCINT and VCCIO. VCCINT pins must always be connected to a 5.0V power supply. VCCINT pins are for input buffers and are "compatible" with both 3.3V and 5.0V inputs. VCCIO pins are for I/O output drives and can be connected for 3.3/5.0V power supply. Open-Collector Output Option This option enables the device output to provide control signals such as an interrupt that can be asserted by any of the several devices.
5
Figure 1. ATF1508AS Macrocell
Programmable Pin-Keeper Option for Inputs and I/Os
The ATF1508AS offers the option of programming all input and I/O pins so that "pin keeper" circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.
Speed/Power Management
The ATF1508AS has several built-in speed and power management features. The ATF1508AS contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 5 - 10 MHz. To further reduce power, each ATF1508AS macrocell has a Reduced Power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option.
Input Diagram
I/O Diagram
6
ATF1508AS/Z
ATF1508AS/Z
All ATF1508s also have an optional power down mode. In this mode, current drops to below 10 mA. When the power down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power down option is selected in the design source file. When enabled, the device goes into power down when either PD1 or PD2 is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin's macrocell may still be used to generate buried foldback and cascade logic signals. All Power-Down AC Characteristic parameters are computed from external input or I/O pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode (Reduced power bit turned on), the reduced power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. The clock must remain stable during TPR.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1508AS fuse patterns. Once programmed, fuse verify is inhibited. However, User Signature and device ID remains accessible.
Programming
ATF1508AS devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for program and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1508AS via the PC. ISP is perfomed by using either a download cable, or a comparable board tester or a simple microprocessor interface. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by Atmel provided Software utilities. ATF1508AS devices can also be programmed using standard 3rd party programmers. With 3rd party programmer the JTAG ISP port can be disabled thereby allowing 4 additional I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details.
Design Software Support
ATF1508AS designs are supported by several third party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.
Power Up Reset
The ATF1508AS has a power-up reset option at two different voltage trip levels when the device is being powered down. Within the fitter, or during a conversion, if the "power-reset" option is turned "on" ( which is the default option), the trip levels during power up or power down is at 2.8V. The user can change this default option from "on" to "off" (within the fitter or specify it as a switch during conversion). When this is done, the voltage trip level during power-down changes from 2.8V to 0.7V. This is to ensure a robust operating environment. The registers in the ATF1508AS are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
ISP Programming Protection
The ATF1508AS has a special feature which locks the device and prevents the inputs and I/O from driving if the programming process is interrupted due to any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin keeper option preserves the former state during device programming. All ATF1508AS devices are initially shipped in the erased state thereby making them ready to use for ISP.
Note: For more information refer to the "Desigining for In-System Programmability with Atmel CPLDs" application note.
7
DC and AC Operating Conditions
Commercial Operating Temperature (Case) VCCINT or VCCIO (5V) Power Supply VCCIO (3.3V) Power Supply 0C - 70C 5V 5% 2.7V - 3.6V Industrial -40C - 85C 5V 10% 2.7V - 3.6V
DC Characteristics
Symbol IIL IIH IOZ Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Tri-State Output Off-State Current VO = VCC or GND Std Mode ICC1 Power Supply Current, Stand-by VCC = Max VIN = 0, VCC "Z" Mode Ind. ICC2 IOS VCCIO VCCIO VIL VIH VOL VOH Note: Power Supply Current, Power Down Mode Output Short Circuit Current Supply Voltage Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VIN = VIH or VIL VCCIO = MIN, IOL = 12 mA VIN = VIH or VIL VCCIO = MIN, IOH = -4.0 mA Com. Ind. 2.4 VCC = Max VIN = 0, VCC VOUT = 0.5V Com. 5.0V Device Output Ind. 3.3V Device Output 4.5 2.7 -0.3 2.0 5.5 3.6 0.8 VCCINT + 0.3 0.45 0.45 V V V V V V V 4.75 "PD" Mode 140 100 -150 5.25 Com. Ind. Com. -40 160 180 100 VIN = VCC Condition Min Typ -2 2 Max -10 10 40 Units A A A mA mA A A A mA V
Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Pin Capacitance
Typ CIN CI/O Note: 8 8 Max 10 10 Units pF pF Conditions VIN = 0V; f = 1.0 MHz VOUT = 0V; f = 1.0 MHz
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin ( high -voltage pin during programming) has a maximum capacitance of 12pf.
8
ATF1508AS/Z
ATF1508AS/Z
Absolute Maximum Ratings*
Temperature Under Bias .................................. -40C to +85C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns.
AC Characteristics
-7 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT tACNT fACNT Parameter Input or Feedback to Non-Registered Output I/O Input or Feedback to Non-Registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold Time of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency 125 125 8 100 3 3 8 100 10 76.9 3 3 3 2.5 7.5 4 4 10 76.9 13 66 7 0 3 0.5 4.5 4 4 3 3 10 6 6 13 66 17 50 Min Max 7.5 7 7 0 3 0.5 5 5 5 4 4 15 8 8 17 50 22 Min -10 Max 10 9 Min 3 3 11 0 3 1.0 8 6 6 4 5 20 10 10 22 -15 Max 15 12 16 0 3 1.5 10 7 7 5 6 25 Min -20 Max 20 16 20 0 3 2 13 Min -25 Max 25 20 Units ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns MHz ns MHz
(continued)
9
AC Characteristics
-7 Symbol FMAX tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Parameter Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF) Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) Output Buffer and Pad Delay (Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF) See ordering information for valid part numbers. Min 166.7 0.5 0.5 1 4 0.8 3 3 2 2 Max Min 125 0.5 0.5 1 5 0.8 5 5 2 1.5 -10 Max Min 100 2 2 2 8 1 6 6 3 4 -15 Max Min 41.7 2 2 2 10 1 7 7 3 5 -20 Max Min 33.3 2 2 2 12 1.2 8 8 4 6 -25 Max Units MHz ns ns ns ns ns ns ns ns ns
tOD2
2.5
2.0
5
6
7
ns
tOD3 Note:
5
5.5
8
10
12
ns
(continued)
Timing Model
U
10
ATF1508AS/Z
ATF1508AS/Z
AC Characteristics
-7 Symbol tZX1 Parameter Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF) Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF) Output Buffer Disable Delay (CL = 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay Reduced-Power Adder(2) 3 2 3 0.5 1 1 3 3 1 2 2 1 10 Min Max 4.0 Min -10 Max 5.0 Min -15 Max 7 Min -20 Max 9 Min -25 Max 10 Units ns
tZX2
4.5
5.5
7
9
10
ns
tZX3 tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA Notes:
9 4 2 3 3 0.5
9 5 4 4 2 2 2 2 5 5 1 3 3 1 11
10 6 5 5 2 2 1 1 6 6 1 4 4 2 13
11 7 6 6 3 2.5 2 2 7 7 1 5 5 2 14
12 8
ns ns ns ns ns ns
2 2 8 8 1 6 6 2 15
ns ns ns ns ns ns ns ns ns
1. See ordering information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode.
Input Test Waveforms and Measurement Levels
Output AC Test Loads:
(3.0V)*
(703 )*
(8060 )*
rR, tF = 1.5 ns typical
Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary).
11
Power Down Mode
The ATF1508AS includes two pins for optional pin controlled power down feature. When this mode is enabled, the PD pin acts as the power down pin. When the PD1 and PD2 pin is high, the device supply current is reduced to less than 3 mA. During power down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs which were in a Hi-Z state at the onset will remain at Hi-Z. During power down, all input signals except the power down pin are blocked. Input and I/O hold latches remain active to insure that pins do not float to indeterminate levels, further reducing system power. The power down pin feature is enabled in the logic design file. Designs using either power down pin may not use the PD pin logic array input. However, all other PD pin as macrocell resources may still be used, including the buried feedback and foldback product term array inputs.
Power Down AC Characteristics(1)(2)
-7 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Notes: Parameter Valid I, I/O Before PD High Valid OE(2) Before PD High Valid Clock
(2)
-10 Max Min 10 10 10 12 12 12 1 1 1 1 15 15 15 1 1 1 1 Max Min 15 15 15
-15 Max Min 20 20 20 25 25 25 1 1 1 1
-20 Max Min 25 25 25 30 30 30 1 1 1 1
-25 Max Units ns ns ns 35 35 35 1 1 1 1 ns ns ns s s s s
Min 7 7 7
Before PD High
I, I/O Don't Care After PD High OE
(2)
Don't Care After PD High
Clock(2) Don't Care After PD High PD Low to Valid I, I/O PD Low to Valid OE (Pin or Term) PD Low to Valid Clock (Pin or Term) PD Low to Valid Output 1. For slow slew outputs, add tSSO. 2. Pin or Product Term.
12
ATF1508AS/Z
ATF1508AS/Z
JTAG-BST Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1508AS. The boundary-scan technique involves the inclusion of a shiftregister stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary scan cell (BSC) in order to support boundary scan testing. The ATF1508AS does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power up. The six JTAG BST modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE. BST on the ATF1508AS is implemented using the Boundary Scan Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third party tool that supports the BSDL format can be used to perform BST on the ATF1508AS. The ATF1508AS also has the option of using four JTAGstandard I/O pins for in-system programming (ISP). The ATF1508AS is programmable through the four JTAG pins using programming compatible with the IEEE JTAG Standard 1149.1. Programming is performed by using 5V TTLlevel programming signals from the JTAG ISP interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. scan cell (BSC) in order to support boundary scan testing as described in detail by IEEE Standard 1149.1. Typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration Pins and Macrocells (except JTAG TAP Pins)
JTAG Boundary Scan Cell (BSC) Testing
The ATF1508AS contains up to 96 I/O pins and 4 input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own boundary
Note: The ATF1508AS has pull-up option on TMS and TDI pins. This feature is selected as a design option.
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BSC Configuration for Macrocell
Pin BSC
TDO
Pin
0 1
DQ Capture DR
TDI
Clock Shift
TDO OEJ
0 0 1 1 DQ DQ
OUTJ
0 0 1 1 DQ DQ
Pin
Capture DR TDI Shift
Update DR Mode Clock
Macrocell BSC
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ATF1508AS/Z
ATF1508AS/Z
PCI Compliance
The ATF1508AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers which are much larger than the traditional TTL drivers.
PCI Voltage-to-Current Curves for +5V Signaling in Pull-Up Mode
Pull Up
PCI Voltage-to-Current Curves for +5V Signaling in Pull-Down Mode
Pull Down
2.4
Voltage
Test Point
2.2
DC drive point
1.4
DC drive point
AC drive point
0.55
Test Point
Voltage
VCC
VCC
AC drive point
-2
-44 Current (mA) -178
3.6
95 Current (mA) 380
PCI DC Characteristics
Symbol VCC VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL LPIN Note: Parameter Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance Leakage Current is without Pin-Keeper off.
= Preliminary
Conditions
Min 4.75 2.0 -0.5
Max 5.25 VCC + 0.5 0.8 70 -70
Units V V V A A V
VIN = 2.7V VIN = 0.5V IOUT = -2 mA IOUT = 3 mA, 6 mA 2.4
0.55 10 12 8 20
V pF pF pF nH
15
PCI AC Characteristics
Symbol IOH(AC) Parameter Switching Current High Conditions 0 < VOUT 1.4 1.4 < VOUT < 2.4 3.1 < VOUT < VCC (Test High) IOL(AC) Switching Current Low VOUT = 3.1V VOUT > 2.2V 2.2 > VOUT > 0 0.1 > VOUT > 0 (Test Point) ICL SLEWR SLEWF Notes: Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.71 -5 < VIN -1 0.4V to 2.4V load 2.4V to 0.4V load -25+(VIN+1)/0.015 0.5 0.5 3.0 3.0 95 VOUT/0.023 Equation B 206 Min -44 -44+(VOUT-1.4)/0.024 Equation A -142 Max Units mA mA mA A mA mA mA mA mA V/ns V/ns
1. Equation A: IOH = 11.9(VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V. 2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
= Preliminary
16
ATF1508AS/Z
ATF1508AS/Z
ATF1508AS Dedicated Pinouts
Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O /GCLK3 I/O / PD (1, 2) I/O / TDI(JTAG) I/O / TMS(JTAG) I/O / TCK(JTAG) I/O / TDO(JTAG) GND VCCINT VCCIO 84-Pin J-Lead 2 1 84 83 81 12,45 14 23 62 71 7,19,32,42, 47,59,72,82 3,43 13,26,38, 53,66,78 100-Pin PQFP 92 91 90 89 87 3,43 6 17 64 75 13,28,40,45, 61,76,88,97 41,93 5,20,36,53,68,84 100-Pin TQFP 90 89 88 87 85 1,41 4 15 62 73 11,26,38,43, 59,74,86,95 39,91 3,18,34,51,66,82 160-Pin PQFP 142 141 140 139 137 63,159 9 22 99 112 17,42,60,66,95, 113,138,148 61,143 8,26,55,79,104,133 1,2,3,4,5,6,7,34,35,36, 37,38,39,40,44,45,46, 47,74,75,76,77,81,82, 83,84,85,86,87,114, 115,116,117,118,119, 120,124,125,126,127, 154,155,156,157 100 96
N/C
-
-
-
# of SIGNAL PINS # USER I/O PINS
68 64
84 80
84 80
OE (1, 2) GCLR GCLK (1, 2, 3) PD (1, 2) TDI, TMS, TCK, TDO GND VCCINT VCCIO
Global OE Pins Global Clear Pin Global Clock Pins Power down pins JTAG pins used for Boundary Scan Testing or In-System Programming Ground Pins VCC pins for the device (+5V - Internal) VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
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ATF1508AS I/O Pinouts
MC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PLB A A A/ PD1 A A A A A A A A A A A A A B B B B B B B B B B B B B B B B/ TDI 84-Pin J-Lead 12 11 10 9 8 6 5 4 22 21 20 18 17 16 15 14 100-Pin PQFP 4 3 2 1 100 99 98 96 95 94 16 15 14 12 11 10 9 8 7 6 100-Pin TQFP 2 1 100 99 98 97 96 94 93 92 14 13 12 10 9 8 7 6 5 4 160-Pin PQFP 160 159 158 153 152 151 150 149 147 146 145 144 21 20 19 18 16 15 14 13 12 11 10 9 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PLB C C C C C C C C C C C C C C C C/ TMS D D D D D D D D D D D D D D D D 84-Pin J-Lead 31 30 29 28 27 25 24 23 41 40 39 37 36 35 34 33 100-Pin PQFP 27 26 25 24 23 22 21 19 18 17 39 38 37 35 34 33 32 31 30 29 100-Pin TQFP 25 24 23 22 21 20 19 17 16 15 37 36 35 33 32 31 30 29 28 27 160-Pin PQFP 41 33 32 31 30 29 28 27 25 24 23 22 59 58 57 56 54 53 52 51 50 49 48 43
18
ATF1508AS/Z
ATF1508AS/Z
ATF1508AS I/O Pinouts (Continued)
MC 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PLB E E E/ PD2 E E E E E E E E E E E E E F F F F F F F F F F F F F F F F/ TCK 84-Pin J-Lead 44 45 46 48 49 50 51 52 54 55 56 57 58 60 61 62 100-Pin PQFP 42 43 44 46 47 48 49 50 51 52 54 55 56 57 58 59 60 62 63 64 100-Pin TQFP 40 41 42 44 45 46 47 48 49 50 52 53 54 55 56 57 58 60 61 62 160-Pin PQFP 62 63 64 65 67 68 69 70 71 72 73 78 80 88 89 90 91 92 93 94 96 97 98 99 MC 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PLB G G G G G G G G G G G G G G G G/ TDO H H H H H H H H H H H H H H H H/ GCLK3 84-Pin J-Lead 63 64 65 67 68 69 70 71 73 74 75 76 77 79 80 81 100-Pin PQFP 65 66 67 69 70 71 72 73 74 75 77 78 79 80 81 82 83 85 86 87 100-Pin TQFP 63 64 65 67 68 69 70 71 72 73 75 76 77 78 79 80 81 83 84 85 160-Pin PQFP 100 101 102 103 105 106 107 108 109 110 111 112 121 122 123 128 129 130 131 132 134 135 136 137
19
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C) STANDARD POWER, MC POWER CONTROL BIT TO NORMAL
200 1.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C) LOW POWER, MC POWER CONTROL BIT TO LOW POWER
175
1.25
ICC (mA)
150
ICC (mA)
4.5 4.75 5 5.25 5.5
1
125
0.75
100
0.5 4.5 4.75 5 5.25 5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C) STANDARD POWER, MC POWER CONTROL BIT TO LOW POWER
200 250 200 150
SUPPLY CURRENT vs. FREQUENCY LOW POWER, MC POWER BIT TO NORMAL (VCC = 5.0V, TA = 25C)
175
ICC (mA)
ICC (mA)
4.5 4.75 5 5.25 5.5
150 100 50
125
100
0 0 5 10 20 50
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (TA = 25C) LOW POWER, MC POWER CONTROL BIT TO NORMAL
1.5 200 150 100 50 0.5 4.5 4.75 5 5.25 5.5 0 0
SUPPLY CURRENT vs. FREQUENCY LOW POWER, MC POWER BIT TO LOW POWER (VCC = 5.0V, TA = 25C)
1.25
ICC (mA)
1
0.75
ICC (mA)
5
10
20
50
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
20
ATF1508AS/Z
ATF1508AS/Z
Ordering Information
tPD (ns) 7.5 tCO1 (ns) 4.5 fMAX (MHz) 166.7 Ordering Code ATF1508AS-7 JC84 ATF1508AS-7 QC100 ATF1508AS-7 AC100 ATF1508AS-7 QC160 ATF1508AS-10 JC84 ATF1508AS-10 QC100 ATF1508AS-10 AC100 ATF1508AS-10 QC160 ATF1508AS-15 JC84 ATF1508AS-15 QC100 ATF1508AS-15 AC100 ATF1508AS-15 QC160 ATF1508AS-15 JI84 ATF1508AS-15 QI100 ATF1508AS-15 AI100 ATF1508AS-15 QI160 ATF1508ASZ-20 JC84 ATF1508ASZ-20 QC100 ATF1508ASZ-20 AC100 ATF1508ASZ-20 QC160 ATF1508ASZ-25 JC84 ATF1508ASZ-25 QC100 ATF1508ASZ-25 AC100 ATF1508ASZ-25 QC160 ATF1508ASZ-25 JI84 ATF1508ASZ-25 QI100 ATF1508ASZ-25 AI100 ATF1508ASZ-25 QI160 Package 84J 100Q1 100A 160Q 84J 100Q1 100A 160Q 84J 100Q1 100A 160Q 84J 100Q1 100A 160Q 84J 100Q1 100A 160Q 84J 100Q1 100A 160Q 84J 100Q1 100A 160Q Operation Range Commercial (0C to 70C)
10
5
125
Commercial (0C to 70C)
15
8
100
Commercial (0C to 70C)
15
8
100
Industrial (-40C to +85C)
20
12
83.3
Commercial (0C to 70C)
25
15
70
Commercial (0C to 70C)
25
15
70
Industrial (-40C to +85C)
Package Type
84J 100Q1 100A 160Q 84-Lead, Plastic J-Leaded Chip Carrier (PLCC) 100-Lead, Plastic Quad Pin Flat Package (PQFP) 100-Lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP) 160-Lead, Plastic Quad Pin Flat Package (PQFP)
21
ATF1508AS/Z
Packaging Information
84J, 84 Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AF
100Q1, 100 Lead, Plastic Gull Wing Quad Flat Package (PQFP) Dimensions in Millimeters and (Inches)
PIN 1 ID
.687(17.44) .667(16.95)
0.026(.65) BSC .016(0.41) .009(0.22)
.792(20.12) .782(19.87) .923(23.45) .904(22.95)
.010(0.25) .004(0.10)
7 0
.556(14.12) .546(13.87)
.134(3.40) MAX
.041(1.03) .004(0.10) MIN .028(0.73)
*Controlling dimension: Millimeters 100A, 100 Lead, Very Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)*
16.25(0.640) 15.75(0.620) PIN 1 ID 0.17(0.007) 0.27(0.011)
160Q, 160 Lead, Plastic Gull Wing Quad Flat Package (PQFP) Dimensions in Millimeters and (Inches)
1.238(31.45) SQ 1.218(30.95)
PIN 1 ID
.016(0.40) .008(0.20) .0256(0.65) BSC
0.56(0.022) 0.44(0.018)
14.10(0.555) 13.90(0.547) 0.20(0.008) 0.10(0.004) 0-7 0.45(0.018) 0.75(0.030) 0.05(0.002) 0.15(0.006)
1.106(28.10)
0.95(0.037) 1.27(0.05)
.009(0.23) .004(0.10)
7 0
1.098(27.90)
SQ
.157(3.97) .127(3.22) .020(0.50) .002(0.05)
.037(0.95) .025(0.65)
*Controlling dimension: Millimeters
*Controlling dimension: Millimeters
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